A Selective Hardware / Compiler Approach for Improving

The widening gap between processor and memory speeds renders data locality optimization a very important issue in compilers. Throughout the years hardware designers and compiler writers focused on optimizing data cache locality using intelligent cache management mechanisms and program-level transformations, respectively. While pure compiler-oriented techniques are quite successful in optimizing codes with regular memory access patterns, they are less successful at improving the locality behavior of non-numerical (integer) programs. On the contrary, the hardware techniques such as cache bypassing and dual/split caches are eeective in codes with irregular access patterns. Until now, there has not been signiicant amount of research investigating the interaction between these optimizations. With this work, we try to ll this gap. We also propose a selective hardware/compiler strategy to optimize cache locality for integer, numerical, and mixed codes. In our framework, the role of the compiler is to identify program regions that can be optimized at compile time using loop and data transformations and to mark the unoptimizable regions with special instructions that activate a state-of-the-art hardware mechanism selectively at run-time. Our results show that our technique can improve program performance by as much as 60% with respect to the base connguration and 17% with respect to non-selective hardware/compiler approach.